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DEVICE SPECIFICATION
DUAL GIGABIT ETHERNET DEVICE DUAL GIGABIT ETHERNET DEVICE GENERAL DESCRIPTION
S2202 S2202
FEATURES
* 1250 MHz (Gigabit Ethernet) operating rate www..com operation - Half rate * Dual Transmitter with phase-locked loop (PLL) clock synthesis from low speed reference * Dual Receiver PLL provides clock and data recovery * Internally series terminated TTL outputs * Low-jitter serial PECL interface * Individual local loopback control * JTAG 1149.1 Boundary scan on low speed I/O signals * Interfaces with coax, twinax, or fiber optics * Single +3.3V supply, 1.85 W power dissipation * Compact 21mm x 21mm 156 TBGA package
The S2202 facilitates high-speed serial transmission of data in a variety of applications including Gigabit Ethernet, serial backplanes, and proprietary point to point links. The chip provides two separate transceivers which are operated individually for a data capacity of >2 Gbps. Each bi-directional channel provides parallel-to-serial and serial-to-parallel conversion, clock generation/recovery, and framing. The on-chip transmit PLL synthesizes the high-speed clock from a low-speed reference. The on-chip dual receive PLL is used for clock recovery and data re-timing on the two independent data inputs. The transmitter and receiver each support differential PECL-compatible I/O for copper or fiber optic component interfaces with excellent signal integrity. Local loopback mode allows for system diagnostics. The chip requires a 3.3V power supply and dissipates 1.85 watts. Figure 1 shows the S2202 and S2002 in a Gigabit Ethernet application. Figure 2 summarizes the input/output signals of the device. Figures 3 and 4 show the transmit and receive block diagrams, respectively.
APPLICATIONS
* * * * * * Ethernet Backbones Workstation Frame buffer Switched networks Data broadcast environments Proprietary extended backplanes
Figure 1. Typical Dual Gigabit Ethernet Application
GE INTERFACE SERIAL BP DRIVER
DUAL GIGABIT ETHERNET INTERFACE
MAC
(ASIC)
S2202 MAC
(ASIC)
S2002
TO SERIAL BACKPLANE
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S2202
Figure 2. S2202 Input/Output Diagram
TRS TMS TCK TDI TDO
DUAL GIGABIT ETHERNET DEVICE
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RESET RATE
REFCLK CLKSEL TMODE TCLKO DINA[0:9] TBCA
10
TXAP/N
TXBP/N
DINB[0:9] TBCB COM_DETA DOUTA[0:9] RBC1/0A
10
RXAP/N
10
COM_DETB DOUTB[0:9] RBC1/0B
10
RXBP/N
TESTMODE TESTMODE1 TESTMODE2 CMODE
LPENA LPENB
2
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DUAL GIGABIT ETHERNET DEVICE
Figure 3. Transmitter Block Diagram
RATE REFCLK www..com CLKSEL
DIN PLL 10x/20x
S2202
REFCLK
TCLKO TMODE TMODE
10 DINA[0:9] FIFO
(input)
10
Shift Reg
TXAP TXAN TXABP
0
1
TBCA
10 DINB[0:9]
FIFO
(input)
10
Shift Reg
TXBP TXBN TXBBP
0
1
TBCB
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S2202
Figure 4. Receiver Block Diagram
TMODE RATE www..com CMODE REFCLK RBC1/0A COM_DETA FIFO
(output) 10
DUAL GIGABIT ETHERNET DEVICE
2
TXABP
10
DOUT CRU SerialParallel
DOUTA[0:9]
Q
RXAP RXAN LPENA
RBC1/0B COM_DETB
2
TXBBP FIFO
(output) 10
10
DOUT CRU SerialParallel
DOUTB[0:9]
RXBP RXBN
LPENB
4
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DUAL GIGABIT ETHERNET DEVICE TRANSMITTER DESCRIPTION
The transmitter section of the S2202 contains a single PLL which is used to generate the serial rate transmit clock for all transmitters. Two channels are provided www..com with a variety of options regarding input clocking and loopback. The transmitters operate at 1.250 GHz, 10 or 20 times the reference clock frequency.
S2202
a system clock. The frequency of this output is constant at the parallel word rate, 1/10 the serial data rate, regardless of whether the reference is provided at 1/10 or 1/20 the serial data rate. This clock can be buffered as required without concern about added delay. There is no phase requirement between TCLKO and TBCx, which is provided back to the S2202, other than that they remain within 3ns of the phase relationship established at reset. The S2202 also supports the traditional REFCLK clocking found in many Gigabit Ethernet applications and is illustrated in Figure 6.
Data Input
The S2202 has been designed to simplify the parallel interface data transfer and provides the utmost in flexibility regarding clocking of parallel data. The S2202 incorporates a unique FIFO structure on both the parallel inputs and the parallel outputs which enables the user to provide a "clean" reference source for the PLL and to accept a separate external clock which is used exclusively to reliably clock data into the device. Data can also be clocked in using the REFCLK. Data is input to each channel of the S2202 nominally as a 10 bit wide word. An input FIFO and a clock input, TBCx, are provided for each channel of the S2202. The device can operate in two different modes. The S2202 can be configured to use either the TCLKx (TCLK MODE) input or the REFCLK input (REFCLK MODE). In TCLK or REFCLK mode, 10 bits of data are clocked into its FIFO with the TBCx provided with each 10 bits. Table 1 provides a summary of the input modes of the S2202. Operation in the TBC MODE makes it easier for users to meet the relatively narrow setup and hold time window required by the 125 Mbps 10-bit interface. The TBC signal is used to clock the data into an internal holding register and the S2202 synchronizes its internal data flow to ensure stable operation. However, regardless of the clock mode, REFCLK is always the VCO reference clock. This facilitates the provision of a clean reference clock resulting in minimum jitter on the serial output. The TBC must be frequency locked to REFCLK, but may have an arbitrary phase relationship. Adjustment of internal timing of the S2202 is performed during reset. Once synchronized, the user must ensure that the timing of the TBC signal does not change by more than 3 ns relative to the REFCLK. Figure 5 demonstrates the flexibility afforded by the S2202. A low jitter reference is provided directly to the S2202 at either 1/10 or 1/20 the serial data rate. This ensures minimum jitter in the synthesized clock used for serial data transmission. A system clock output at the parallel word rate, TCLKO, is derived from the PLL and provided to the upstream circuit as
Half Rate Operation
The S2202 supports full and half rate operation for all modes of operation. When RATE is LOW, the S2202 serial data rate equals the VCO frequency. When RATE is HIGH, the VCO is divided by 2 before being provided to the chip. Thus the S2202 can support Gigabit Ethernet and serial backplane functions at both full and half the VCO rate. See Table 3.
Parallel to Serial Conversion
The 10-bit parallel data handled by the S2202 device should be from a DC-balanced encoding scheme, such as the 8B/10B transmission code, in which information to be transmitted is encoded, 8 bits at a time, into a 10-bit transmission character and must be compliant with IEEE 802.3z Gigabit Ethernet. The 8B/10B transmission code includes serial encoding and decoding rules, special characters, and error control. Information is encoded, 8 bits at a time, into a 10 bit transmission character. The characters defined by this code ensure that short run lengths and enough transitions are present in the serial bit stream to make clock recovery possible at the receiver. The encoding also greatly increases the likelihood of detecting any single or multiple errors that might occur during the transmission and reception of data1. Table 1. Input Modes
TMODE 0 1 Operation REFCLK Mode. REFCLK used to clock data into FIFOs for all channels. TBC Mode. TBCx used to clock data into FIFOs for all channels.
Note that internal synchronization of FIFOs is performed upon de-assertion of RESET.
1. A.X. Widner and P.A. Franaszek, "A Byte-Oriented DC Balanced (0,4) 8B/10B Transmission Code," IBM Research Report RC9391, May 1982.
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S2202
Table 2 identifies the mapping of the 8B/10B characters to the data inputs of the S2202. The S2202 will serialize the parallel data for each channel and will transmit bit "a" or DIN[0] first.
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DUAL GIGABIT ETHERNET DEVICE
Reference Clock Input
The reference clock input must be supplied with a low-jitter clock source. All reference clocks in a system must be within 200 ppm of each other to ensure that the clock recovery units can lock to the serial data. Gigabit Ethernet applications may require tighter tolerances. The frequency of the reference clock must be either 1/10 the serial data rate, CLKSEL = 0, or 1/20 the serial data rate, CLKSEL=1. In both cases the frequency of the parallel word rate output, TCLKO, is constant at 1/10 the serial data rate. See Table 3.
Frequency Synthesizer (PLL)
The S2202 synthesizes a serial transmit clock from the reference signal. Upon startup, the S2202 will obtain phase and frequency lock within 2500 bit times after the start of receiving reference clock inputs. Reliable locking of the transmit PLL is assured, but a lock-detect output is NOT provided.
Table 2. Data to 8B/10B Alphabetic Representation
Data Byte DIN[0:9] or DOUT[0:9] 8B/10B Alphanumeric Representation 0123456789 abcde i f gh j
Serial Data Outputs
The S2202 provides LVPECL level serial outputs. The serial outputs do not require output pulldown resistors. Outputs are designed to perform optimally when AC-coupled.
Table 3. Operating Rates
RATE 0 0 1 1 CLKSEL 0 1 0 1 REFCLK Frequency 125 MHz 62.5 MHz 62.5 MHz 31.25 MHz Serial Output Rate 1250 MHz 1250 MHz 625 MHz 625 MHz TCLKO Frequency 125 MHz 125 MHz 62.5 MHz 62.5 MHz
Transmit FIFO Initialization
The transmit FIFO must be initialized after stable delivery of data and TBC to the parallel interface, and before entering the normal operational state of the circuit. FIFO initialization is performed upon the de-assertion of the RESET signal. TCLKO will oper. ate normally regardless of the state of RESET.
Figure 5. DIN Data Clocking with TBC
125 MHz or 62.5 MHz REF OSCILLATOR
Figure 6. GE DIN Clocking with REFCLK
125 MHz REF OSCILLATOR
REFCLK TCLKO
PLL
TCLKO
REFCLK
PLL
DINx[0:9]
DINx[0:9]
TBCx
TBCx
MAC ASIC
S2202
MAC ASIC
S2202
6
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DUAL GIGABIT ETHERNET DEVICE RECEIVER DESCRIPTION
Each receiver channel is designed to implement a Serial Backplane receiver function through the physical layer. A block diagram showing the basic funcwww..com tion is provided in Figure 4. Whenever a signal is present, the receiver attempts to recover the serial clock from the received data stream. After acquiring bit synchronization, the S2202 searches the serial bit stream for the occurrence of a K28.5 character on which to perform word synchronization. Once synchronization on both bit and word boundaries is achieved, the receiver provides the word-aligned data on its parallel outputs.
S2202
tive ones or zeros across 12 parallel words. Thus 119 or less consecutive ones or zeros does not cause signal loss, 129 or more causes signal loss, and 120-128 may or may not, depending on how the data aligns across byte boundaries. If both the off-frequency detect circuitry test and the run-length test are satisfied, the CRU will attempt to lock to the incoming data. It is possible for the run length test to be satisfied due to noise on the inputs, even if no signal is present. In this case the receiver VCO will maintain frequency accuracy to within 100 ppm of the target rate as determined by REFCLK. In any transfer of PLL control from the serial data to the reference clock, the RBC1/0x outputs remain phase continuous and glitch free, assuring the integrity of downstream clocking.
Data Input
A differential input receiver is provided for each channel of the S2202. Each channel has a loopback mode in which the serial data from the transmitter replaces external serial data. The loopback function for each channel is enabled by its respective LPEN input. The high speed serial inputs to the S2202 are internally biased to VDD-1.3V. All that is required externally are AC-coupling and line-to-line differential termination.
Reference Clock Input
A single reference clock, which serves both transmitter and receiver, must be provided from a low jitter clock source. The frequency of the received data stream (divided-by -10 or -20) must be within 200 ppm of the reference clock to ensure reliable locking of the receiver PLL.
Clock Recovery Function
Clock recovery is performed on the input data stream for each channel of the S2202. The receiver PLL has been optimized for the anticipated needs of Serial Backplane systems. A simple state machine in the clock recovery macro decides whether to acquire lock from the serial data input or from the reference clock. The decision is based upon the frequency and run length of the serial data inputs. If at any time the frequency or run length checks are violated, the state machine forces the VCO to lock to the reference clock. This allows the VCO to maintain the correct frequency in the absence of data. The "lock to reference" frequency criteria ensure that the S2202 will respond to variations in the serial data input frequency (compared to the reference frequency). The new lock state is dependent upon the current lock state, as shown in Table 4. The run-length criteria ensure that the S2202 will respond appropriately and quickly to a loss of signal. The run-length checker flags a condition of consecu-
Serial-to-Parallel Conversion
Once bit synchronization has been attained by the S2202 CRU, the S2202 must synchronize to the 10 bit word boundary. Word synchronization in the S2202 is accomplished by detecting and aligning to the 8B/10B K28.5 codeword. The S2202 will detect and byte-align to either polarity of the K28.5. Each channel of the S2202 will detect and align to a K28.5 anywhere in the data stream. For TCLK or REFCLK mode operation, the presence of a K28.5 is indicated for each channel by the assertion of the COM_DETx signal.
Table 4. Lock to Reference Frequency Criteria
Current Lock State PLL Frequency (vs. REFCLK) < 488 ppm Locked 488 to 732 ppm > 732 ppm < 244 ppm Unlocked 244 to 366 ppm > 366 ppm New Lock State Locked Undetermined Unlocked Locked Undetermined Unlocked
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S2202
Data Output
Data is output on the DOUT[0:9] outputs. The COM_DET signal is used to indicate the reception of a valid K28.5 character. The S2202 TTL outputs are optimized to drive 65 line impedances. Internal source matching provides good performance on unterminated lines of reasonable length.
DUAL GIGABIT ETHERNET DEVICE OTHER OPERATING MODES
Operating Frequency Rate
The S2202 is designed to operate at the Gigabit Ethernet rate of 1.250 GHz.
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Loopback Mode
When loopback mode is enabled, the serial data from the transmitter is provided to the serial input of the receiver, as shown in Figure 7. This provides the ability to perform system diagnostics and off-line testing of the interface to verify the integrity of the serial channel. Loopback mode is enabled independently for each channel using its respective loopback-enable input, LPEN.
Parallel Output Clock Rate
Two output clock modes are supported, as shown in Table 5. When CMODE is High, a complementary TTL clock at the data rate is provided on the RBC1/ 0x outputs. Data should be clocked on the rising edge of RBC1x. When CMODE is Low, a complementary TTL clock at half the data rate is provided. Data should be latched on the rising edge of RBC1x and the rising edge of RBC0x.
TEST MODES
The RESET pin is used to initialize the Transmit FIFOs and must be asserted (LOW) prior to entering the normal operational state (see section Transmit FIFO Initialization).
Table 5. Output Clock Mode
Mode Half Clock Mode Full Clock Mode
CMODE 0 1
RBC1/0x Freq
Figure 7. S2202 Diagnostic Loopback Operation
62.5 MHz 125 MHz
CSU
In Gigabit Ethernet applications, multiple consecutive K28.5 characters cannot be generated. However, for serial backplane applications this can occur. The S2202 must be able to operate properly when multiple K28.5 characters are received. After the first K28.5 is detected and aligned, the RBC1/0x clock will operate without glitches or loss of cycles.
CRU
Note: Serial output data remains active during loopback operation to enable other system tests to be performed.
External Receiver Clocking
An external clock can be provided to the S2202 to clock the parallel receive data, DOUT[0:9], out of the device. External Clock mode is enabled when TMODE = Low. Table 5A describes the receiver output clocking options available. When TBCA is used as the output clock source, the REFCLK and TBCA frequency must equal the parallel word rate, CLKSEL = Low. The RBC1/0x outputs will provide a buffered copy of the output clock.
Table 5A. S2202 Data Clocking
TMODE 0 1 Input Clock Source REFCLK TBCx Output Clock Source TBCA RBCx
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July 16, 1999 / Revision A
DUAL GIGABIT ETHERNET DEVICE JTAG TESTING
The JTAG implementation for the S2202 is compliant with the IEEE1149.1 requirements. JTAG is used to test the connectivity of the pins on the chip. The www..com TAP, (Test Access Port), provides access to the test logic of the chip. When TRST is asserted the TAP is initialized. TAP is a state machine that is controlled by TMS. The test instruction and data are loaded through TDI on the rising edge of TCK. When TMS is high the test instruction is loaded into the instruction register. When TMS is low the test data is loaded into the data register. TDO changes on the falling edge of TCK. All input pins, including clocks, that have boundary scan are observe only. They can be sampled in either normal operational or test mode. All output pins that have boundary scan, are observe and control. They can be sampled as they are driven out of the chip in normal operational mode, and they can be driven out of the chip in test mode using the Extest instruction. Since JTAG testing operates only on digital signals there are some pins with analog signals that JTAG does not cover. The JTAG implementation has the three required instruction, Bypass, Extest, and Sample/Preload. Instruction BYPASS EXTEST SAMPLE/PRELOAD ID CODE Code 11 00 01 10
S2202
JTAG Instruction Description:
The BYPASS register contains a single shift-register stage and is used to provide a minimum-length serial path between the TDI and TDO pins of a component when no test operation of that component is required. This allows more rapid movement of test data to and from other components on a board that are required to perform test operations. The EXTEST instruction allows testing of off-chip circuitry and board level interconnections. Data would typically be loaded onto the latched parallel outputs of boundary-scan shift-register stages using the SAMPLE/PRELOAD instruction prior to selection of the EXTEST instruction. The SAMPLE/PRELOAD instruction allows a snapshot of the normal operation of the component to be taken and examined. It also allows data values to be loaded onto the latched parallel outputs of the boundary-scan shift register prior to selection of the other boundary-scan test instructions. The following table provides a list of the pins that are JTAG tested. Each port has a boundary scan register (BSR), unless otherwise noted. The following features are described: the JTAG mode of each register (input, output2, or internal (refers to an internal package pin)), the direction of the port if it has a boundary scan register (in or out), and the position of this register on the scan chain.
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S2202
Table 6. JTAG Pin Assignments
S2202 Pin Name TESTMODE2 CMODE Core_Scan Port Name testmode_2 cmode testmode_0 JTAG Mode Input Input Input Internal LPENB lpenb Input Internal LPENA CLKSEL TMODE lpena clksel tmode Input Input Input Internal RESET REFCLK TCLKO reset refclk transmit_clk_ buf_out testmode_1 tdatain_b (9) tdatain_b (8) tdatain_b (7) tdatain_b (6) tdatain_b (5) tdatain_b (4) tdatain_b (3) tdatain_b (2) tdatain_b (1) tdatain_b (0) tclkb Input Input Output2 Internal TESTMODE1 DINB9 DINB8 DINB7 DINB6 DINB5 DINB4 DINB3 DINB2 DINB1 DINB0 TBCB Input Input Input Input Input Input Input Input Input Input Input Input Internal DINA9 DINA8 DINA7 DINA6 DINA5 DINA4 DINA3 DINA2 DINA1 DINA0 TBCA tdatain_a (9) tdatain_a (8) tdatain_a (7) tdatain_a (6) tdatain_a (5) tdatain_a (4) tdatain_a (3) tdatain_a (2) tdatain_a (1) tdatain_a (0) tclka Input Input Input Input Input Input Input Input Input Input Input Internal RBC1B RBC0B DOUTB7 DOUTB6 DOUTB5 DOUTB4 DOUTB3 rcbp rcbn rdataout_b (7) rdataout_b (6) rdataout_b (5) rdataout_b (4) rdataout_b (3) Output2 Output2 Output2 Output2 Output2 Output2 Output2 In Routing Out 0 1 2 3 4 5 6 7 8 9 10 11 13-22 23 24 25 26 27 28 29 30 31 32 33 34 35-45 46 47 48 49 50 51 52 53 54 55 56 12 57-69 70 71 72 73 74 75 76
DUAL GIGABIT ETHERNET DEVICE
S2202 Pin Name DOUTB2 DOUTB1 DOUTB0 DOUTB9 COM_DETB DOUTB8 Core_Scan Port Name rdataout_b (2) rdataout_b (1) rdataout_b (0) rdataout_b (9) eofd_b rdataout_b (8) JTAG Mode Output2 Output2 Output2 Output2 Output2 Output2 Internal RBC1A RBC0A DOUTA9 DOUTA7 DOUTA6 DOUTA5 DOUTA4 DOUTA3 DOUTA2 DOUTA1 DOUTA0 COM_DETA DOUTA8 rcap rcan rdataout_a (9) rdataout_a (7) rdataout_a (6) rdataout_a (5) rdataout_a (4) rdataout_a (3) rdataout_a (2) rdataout_a (1) rdataout_a (0) eofd_a rdataout_a (8) Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output2 Internal JTAG Control Pins (Ports that do not have a Boundary Scan Register) TCK TDI TDO TMS TRS jtag_tck jtag_tdi jtag_tdo jtag_tms jtag_trs Routing Out 77 78 79 80 81 82 83-95 96 97 98 99 100 101 102 103 104 105 106 107 108 109
In
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TESTMODE
Pins not JTAG Tested TXAP TXAN TXBP TXBN RATE RXAP RXAN RXBP RXBN -
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Table 7. Transmitter Input Pin Assignment and Descriptions
Pin Name
www..com DINA9
S2202
Level TTL
I/O I
Pin # T15 R13 P12 T14 R12 P11 T13 R11 T12 P10 R10
Description Transmit Data for Channel A. Parallel data on this bus is clocked in on the rising edge of TBCA or REFCLK.
DINA8 DINA7 DINA6 DINA5 DINA4 DINA3 DINA2 DINA1 DINA0 TBCA TTL I
Transmit Byte Clock A. When TMODE is High, this signal is used to clock Data on DINA[0:9] into the S2202. When TMODE is Low, TBCA is ignored. Transmit Data for Channel B. Parallel data on this bus is clocked in on the rising edge of TBCB or REFCLK.
DINB9 DINB8 DINB7 DINB6 DINB5 DINB4 DINB3 DINB2 DINB1 DINB0 TBCB
TTL
I
L14 M16 M15 M14 N16 N15 N14 P16 P15 R16 P14
TTL
I
Transmit Byte Clock B. When TMODE is High, this signal is used to clock Data on DINB[0:9] into the S2202. When TMODE is Low, TBCB is ignored.
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S2202
Table 8. Transmitter Output Signals
Pin Name
www..com TXAP
DUAL GIGABIT ETHERNET DEVICE
Level Diff. LVPECL Diff. LVPECL TTL
I/O O
Pin # D16 E16 G16 F16 K15
Description High speed serial outputs for Channel A.
TXAN TXBP TXBN TCLKO
O
High speed serial outputs for Channel B.
O
TTL Output Clock at the Parallel data rate. This clock is provided for use by up-stream circuitry.
Table 9. Mode Control Signals
Pin Name TESTMODE Level TTL I/O I Pin # D3 Description Test Mode Control. Keep Low for normal operation.
TESTMODE1
TTL
I
L15
Test Mode Control. Keep Low for normal operation.
TESTMODE2
TTL
I
C4
Test Mode Control. Keep Low for normal operation.
TMODE
TTL
I
A13
Transfer Mode Control. Controls the source of the clock used to input and output data to and from the S2202. When TMODE is Low, REFCLK is used to clock data on DINx[0:9] into the S2202. TBCA is used to clock parallel data DOUTx[0:9] out of the device. When TMODE is High, the TBCx inputs are used to clock data into their respective channels. The output clocks are derived from the receivers' CRUs. REFCLK Select Input. This signal configures the PLL for the appropriate REFCLK frequency. When CLKSEL = 0, the REFCLK frequency equals the parallel word rate. When CLKSEL = 1, the REFCLK frequency is half the parallel data rate. Reference Clock is used for the transmit VCO and frequency check for the clock recovered from the receiver serial data. When Low, the S2202 is held in reset. The receiver PLL is forced to lock to the REFCLK. The FIFOs are initialized on the rising edge of RESET. When High, the S2202 operates normally. When Low, the S2202 operates with the serial output rate equal to the VCO frequency. When High, the S2202 operates with the VCO internally divided by 2 for all functions.
CLKSEL
TTL
I
B11
REFCLK
TTL
I
J14
RESET
TTL
I
B15
RATE
TTL
I
C11
Note: All TTL inputs except REFCLK have internal pull-up networks.
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DUAL GIGABIT ETHERNET DEVICE
Table 10. Receiver Output Pin Assignment and Descriptions
Pin Name
www..com DOUTA9
S2202
Level TTL
I/O O
Pin # J2 G2 L2 L1 K2 K1 J3 J1 H3 H2 G1
Description Channel A Receiver Data Outputs. Parallel data on this bus is valid on the rising edge of RBC1A in full clock mode and valid on the rising edge of both RBC1A and RBC0A in half clock mode.
DOUTA8 DOUTA7 DOUTA6 DOUTA5 DOUTA4 DOUTA3 DOUTA2 DOUTA1 DOUTA0 COM_DETA TTL O
Channel A Comma Detect. A High on this output indicates that a valid K28.5 has been detected and is present on the parallel data outputs DOUTA[0:9]. Receive Byte Clocks. Parallel receive data, DOUTA[0:9] and COM_DETA are valid on the rising edge of RBC1A when in full clock mode and valid on the rising edge of both RBC1A and RBC0A in half clock mode. Channel B Receiver Data Outputs. Parallel data on this bus is valid on the rising edge of RBC1B in full clock mode and valid on the rising edge of both RBC1B and RBC0B in half clock mode.
RBC1A RBC0A
TTL
O
M1 L3
DOUTB9 DOUTB8 DOUTB7 DOUTB6 DOUTB5 DOUTB4 DOUTB3 DOUTB2 DOUTB1 DOUTB0 COM_DETB
TTL
O
P4 P2 P8 T5 R6 P6 R5 T3 P5 R3 P3
TTL
O
Channel B Comma Detect. A High on this output indicates that a valid K28.5 has been detected and is present on the parallel data outputs DOUTB[0:9]. Receive Byte Clocks. Parallel receive data, DOUTB[0:9] and COM_DETB are valid on the rising edge of RBC1B when in full clock mode and valid on the rising edge of both RBC1B and RBC0B in half clock mode.
RBC1B RBC0B
TTL
O
R7 P7
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S2202
Table 11. Receiver Input Pin Assignment and Descriptions
Pin Name
www..com RXAP
DUAL GIGABIT ETHERNET DEVICE
Level Diff. LVPECL Diff. LVPECL
I/O I
Pin # A3 A4 A8 A9
Description Differential LVPECL compatible inputs for channel A. RXAP is the positive input, RXAN is the negative. Internally biased to VDD -1.3V for AC coupled applications. Differential LVPECL compatible inputs for channel B. RXBP is the positive input, RXBN is the negative. Internally biased to VDD -1.3V for AC coupled applications.
RXAN RXBP RXBN
I
Table 12. Receiver Control Signals
Pin Name LPENA LPENB CMODE Level TTL I/ O I Pin # C14 H14 C2 Description Loopback Enable. When Low, input source is the high speed serial input for each channel. When High, the serial output for each channel is looped back to its input. Clock Mode Control. When Low, the parallel output clocks (RBC1/0x) rate is equal to 1/2 the data rate. When High, the parallel output clocks (RBC1/0x) rate is equal to the data rate.
TTL
I
Note: All TTL inputs except REFCLK have internal pull-up networks.
Table 13. Power and Ground Signals
Pin Name VDDA Qty. 4 Pin # A6, B4, B13, C8 A2, B8, C13 B12, C6, C9 Analog Power (VDD) low noise. Description
VSSA
3
Analog Ground (VSS).
VDD
3
Power for High Speed Circuitry (VDD).
VSS VSSSUB
8
A7, A11, Ground for High Speed Circuitry (VSS). A12, A14, B5, B7, C7, C12
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Table 13. Power and Ground Signals (Continued)
Pin Name
www..com PECLPWR
S2202
Qty. 4
Pin # D15, F15, PECL Power (VDD) G14, H15 C16 J16 B2, C1, D2, J15, N1, P9 C3, D1, E2, E3, K16, R1, T1, T11 F1, G3, H1, M2, P1, R4, R8, T7 E1, F2, F3, K3, M3, N3, R2, T2, T4, T8 A16 B1 PECL Ground (VSS)
Description
PECLGND
2
DIGPWR
6
Core Circuitry Power (VDD)
DIGGND
8
Core Circuitry Ground (VSS)
TTLPWR
8
Power for TTL I/O (VDD)
TTLGND
10
Ground for TTL I/O (VSS)
PWR
2
Power
GND
5
K14, L16, Ground P13, R14, T16 A15 B14 Pins for external loop filter capacitor
CAP1 CAP2 NC
2
18
A1, A5, Not Connected. Used as test pins. Do Not Connect. B6, B9, B16, C5, C15, D14, E14, E15, F14, G15, N2, R9, R15, T6, T9, T10
July 16, 1999 / Revision A
15
S2202
Table 14. JTAG Test Signals
Pin Name
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DUAL GIGABIT ETHERNET DEVICE
Level
I/O
Pin #
Description
TMS
TT L
I
A10
Test Mode Select. Enables JTAG testing of device.
TCK
TTL
I
B10
Test Clock. JTAG test clock.
TDI
TTL
I O TRISTATE I
C10
Test Data In. JTAG data input. Test Data Out. JTAG data output. Can be high impedance under JTAG controller command. Test Reset. Resets JTAG test state machine.
TDO
TTL
H16
TRS
TTL
B3
16
July 16, 1999 / Revision A
DUAL GIGABIT ETHERNET DEVICE
Figure 8. S2202 Pinout (Bottom View)
A B C D E F G H J K L M N P R
S2202
T
www..com 1 NC
PWR
DIGPWR
DIGGND
TTLGND
TTLPWR
COM_ DETA
TTLPWR
DOUTA2
DOUTA4
DOUTA6
RBC1A
DIGPWR
TTLPWR
DIGGND
DIGGND
2
VSSA
DIGPWR
CMODE
DIGPWR
DIGGND
TTLGND
DOUTA8
DOUTA0
DOUTA9
DOUTA5
DOUTA7
TTLPWR
NC
DOUTB8
TTLGND
TTLGND
3
RXAP
TRS
DIGGND
TEST MODE
DIGGND
TTLGND
TTLPWR
DOUTA1
DOUTA3
TTLGND
RBC0A
TTLGND
TTLGND
COM_ DETB
DOUTB0
DOUTB2
4
RXAN
VDDA
TEST MODE2
DOUTB9
TTLPWR
TTLGND
5
NC
VSSSUB
NC
DOUTB1
DOUTB3
DOUTB6
6
VDDA
NC
VDD
DOUTB4
DOUTB5
NC
7
VSSSUB
VSS
VSS
RBC0B
RBC1B
TTLPWR
8
RXBP
VSS A
VDDA
DOUTB7
TTLPWR
TTLGND
9
RXBN
NC
VDD
DIGPWR
NC
NC
10
TMS
TCK
TDI
DINA0
TBCA
NC
11
VSS
CLKSEL
RATE
DINA4
DINA2
DIGGND
12
VSSSUB
VDD
VSSSUB
DINA7
DINA5
DINA1
13
TMODE
VDDA
VSS A
GND
DINA8
DINA3
14
VSS
CAP2
LPEN A
NC
NC
NC
P E CL PWR
L P E NB
REFCLK
GND
DINB9
DINB6
DINB3
TBCB
GND
DINA6
15
CAP1
RESET
NC
PECL PWR
NC
P E CL PWR
NC
PECL PWR
DIGPWR
TCLKO
TEST MODE1
DINB7
DINB4
DINB1
NC
DINA9
16
PWR
NC
PECLGND
TXAP
TXAN
TXBN
TXBP
TDO
PECLGND DIGGND
GND
DINB8
DINB5
DINB2
DINB0
GND
Note: NC used as test pins. Do Not Connect.
July 16, 1999 / Revision A
17
S2202
Figure 9. S2202 Pinout (Top View)
T R P N M L K J H G
DUAL GIGABIT ETHERNET DEVICE
F
E
D
C
B
A
www..com TTLPWR DIGPWR DIGGND DIGGND
RBC1A
DOUTA6
DOUTA4
DOUTA2
TTLPWR
COM_ DETA
TTLPWR
TTLGND
DIGGND
DIGPWR
PWR
NC
1
TTLGND
TTLGND
DOUTB8
NC
TTLPWR
DOUTA7
DOUTA5
DOUTA9
DOUTA0
DOUTA8
TTLGND
DIGGND
DIGPWR
CMODE
DIGPWR
VSSA
2
DOUTB2
DOUTB0
COM_ DETB
TTLGND
TTLGND
RBC0A
TTLGND
DOUTA3
DOUTA1
TTLPWR
TTLGND
DIGGND
TE S T MODE
DIGGND
TRS
RXAP
3
TTLGND
TTLPWR
DOUTB9
TEST MODE2
VDDA
RXAN
4
DOUTB6
DOUTB3
DOUTB1
NC
VSSSUB
NC
5
NC
DOUTB5
DOUTB4
VDD
NC
VDDA
6
TTLPWR
RBC1B
RBC0B
VSS
VSS
VSSSUB
7
TTLGND
TTLPWR
DOUTB7
VDDA
VSS A
RXBP
8
NC
NC
DIGPWR
VDD
NC
RXBN
9
NC
TBCA
DINA0
TDI
TCK
TMS
10
DIGGND
DINA2
DINA4
RATE
CLKSEL
VSS
11
DINA1
DINA5
DINA7
VSSSUB
VDD
VSSSUB
12
DINA3
DINA8
GND
VSSA
VDDA
TMODE
13
DINA6
GND
TBCB
DINB3
DINB6
DINB9
GND
REFCLK
LPENB
PECL PWR
NC
NC
NC
LPENA
CAP2
VSS
14
DINA9
NC
DINB1
DINB4
DINB7
TEST MODE1
TCLKO
DIGPWR
PECL PWR
NC
PECL PWR
NC
PECL PWR
NC
RESET
CAP1
15
GND
DINB0
DINB2
DINB5
DINB8
GND
DIGGND PECLGND
TDO
TXBP
TXBN
TX A N
TXAP
PECLGND
NC
PWR
16
Note: NC used as test pins. Do Not Connect.
18
July 16, 1999 / Revision A
DUAL GIGABIT ETHERNET DEVICE
Figure 10. Compact 21mm x 21mm 156 TBGA Package
S2202
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Thermal Management
Device S2202
ja 15C/W
jc 1.0C/W
July 16, 1999 / Revision A
19
S2202
Figure 11. Transmitter Timing (REFCLK Mode, TMODE = 0)
REFCLK
w w w . d a t a s h e e t 4 u . c o m
DUAL GIGABIT ETHERNET DEVICE
DINx[0:9] T1 T2
SERIAL DATA OUT
Table 15. S2202 Transmitter Timing (REFCLK Mode, TMODE = 0)
Parameters T1 T2 Description Data Setup w.r.t. REFCLK Data Hold w.r.t. REFCLK Min 0.5 1.5 Max Units ns ns Conditions See Note 1. --
1. All AC measurements are made from the reference voltage levels of the clock (1.4V) to the valid input or output data levels (.8V or 2.0V).
Figure 12. Transmitter Timing (TBC Mode, TMODE = 1)
TBCx
DINx[0:9] T1 T2
SERIAL DATA OUT
Table 16. S2202 Transmitter Timing (TBC Mode, TMODE = 1)
Parameters T1 T2 Description Data Setup w.r.t. TBC Data Hold w.r.t. TBC Phase drift between TBCx and REFCLK Min 1.0 0.5 -3 Max +3 Units ns ns ns Conditions See Note 1.
1. All AC measurements are made from the reference voltage levels of the clock (1.4V) to the valid input or output data levels (.8V or 2.0V).
20
July 16, 1999 / Revision A
DUAL GIGABIT ETHERNET DEVICE
Table 17. S2202 Receiver Timing (Full and Half Clock Mode)
Parameters T3 www..com T4 T5 T6 T7 TR1, TF1 TR0, TF0 TDR, TDF Duty Cycle Description Data Setup w.r.t. RBC1/0x Data Hold w.r.t. RBC1/0x Data Setup w.r.t. RBC1/0x Data Hold w.r.t. RBC1/0x Time from RBC1x rise to RBC0x rise RBC1x Rise and Fall Times RBC0x Rise and Fall Times DOUTx Rise and Fall Times RBC1/0x Duty Cycle 40 Min 2.5 2.5 2.5 2.5 7.5 8.5 2.4 2.4 2.4 60 Max Units ns ns ns ns ns ns ns ns % Conditions at 1.25 Gbps TMODE = 1 TMODE = 1 at 1.25 Gbps TMODE = 1 TMODE = 1 at 1.25 Gbps
1,2 1,2 1,2
S2202
See note 2. See Figure 18. See note 2. See Figure 18. See note 2. See Figure 18. See note 1.
1. Measurements made from the reference voltage levels of the clock (1.4V) to the valid input or output data levels (.8V or 2.0V). 2. TTL/CMOS AC timing measurements are assumed to have an output load of 10pf.
Table 18. Receiver Timing (External Clock Mode)
Parameters T8 Description TBCA to DOUTx Propagation Delay Min 3.0 Max 8.0 Units ns Conditions 10 pf load capacitance at the end of a 3 inch 50 transmission line.
1. Measurements made from the reference voltage levels of the clock (1.4V) to the valid input or output data levels (.8V or 2.0V).
July 16, 1999 / Revision A
21
S2202
Figure 13. Receiver Timing (Full Clock Mode, CMODE = 1)
SERIAL DATA IN
DUAL GIGABIT ETHERNET DEVICE
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RBC0x
RBC1x
DOUTx[0:9], COM_DETx T3 T4
Figure 14. Receiver Timing (Half Clock Mode, CMODE = 0)
SERIAL DATA IN
RBC0x
RBC1x
DOUTx[0:9], COM_DETx T5 T6 T7 T5 T6
Figure 15. Receiver Timing (External Clock Mode) (TBCA to DATA Propagation Delay, TMODE = 0)
SERIAL DATA IN
TBCA (Input)
DOUTx[0:9], COM_DETx T8
22
July 16, 1999 / Revision A
DUAL GIGABIT ETHERNET DEVICE
Figure 16. TCLKO Timing
S2202
REFCLK www..com T9 TCLKO
Table 19. S2202 Transmitter (TCLKO Timing)
Parameters T9 Description TCLKO w.r.t. REFCLK TCLKO Duty Cycle
Note: Measurements are made at 1.4V level of clocks.
Min 1.0 45%
Max 6.5 55%
Units ns %
Conditions
July 16, 1999 / Revision A
23
S2202
Table 20. Absolute Maximum Ratings
Parameter Storage Temperature
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DUAL GIGABIT ETHERNET DEVICE
Min -65 -0.5 -0.5 0
Typ
Max 150 +5.0 3.47 VDD 8 8 25
Units C V V V mA mA mA
Voltage on VDD with Respect to GND Voltage on any TTL Input Pin Voltage on any PECL Input Pin TTL Output Sink Current TTL Output Source Current High Speed PECL Output Source Current ESD Sensitivity
1
Over 500 V
1. Human body model.
Table 21. Recommended Operating Conditions
Parameter Ambient Temperature Under Bias Junction Temperature Under Bias Voltage on any Power Pin with respect to GND/VSS Voltage on TTL Input Pin Voltage on any PECL Input Pin 3.13 0 VDD -2V 3.3 Min 0 Typ Max 70 130 3.47 3.47 VDD Units C C V V V
Table 22. Reference Clock Requirements
Parameters FT TD1-2 TRCR, TRCF -- Description Frequency Tolerance Symmetry REFCLK Rise and Fall Time Jitter Min -100 40 Max +100 60 2 80 Units ppm % ns ps Duty Cycle at 50% pt. 20% - 80%. Peak-to-Peak, to maintain 77% eye opening. Conditions
24
July 16, 1999 / Revision A
DUAL GIGABIT ETHERNET DEVICE
Table 23. Serial Data Timing, Transmit Outputs
Parameters Total Jitter
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S2202
Description Serial Data Output total jitter Serial Data Output deterministic jitter Serial Data Output rise and fall time
Min
Typ
Max 192 80 300
Units ps ps ps
Comments Peak-to-Peak. Peak-to-Peak. 20% - 80%. See Figure 17.
TDJ
TSR, TSF
Table 24. Serial Data Timing, Receive Inputs
Parameters TLOCK (Startup) TDJ Input Jitter Tolerance RSR, RSF Description Startup Acquisition Lock Time at 1.25 Gbps Deterministic Input Jitter Tolerance Serial Data Input total jitter tolerance Serial Data Input rise and fall time 370 599 330 Min Typ Max 2.5 Units s ps ps ps Peak-to-Peak, as specified by IEEE 802.3z. 20% - 80%. See Figure 17. Comments 8B/10B idle pattern sample basis, from device start up.
Table 25. DC Characteristics
Parameters VOH VOL VIH VIL IIH IIL IDD PD VDIFF VOUT CIN Description Output High Voltage (TTL) Output Low Voltage (TTL) Input High Voltage (TTL) Input Low Voltage (TTL) Input High Current (TTL) Input Low Current (TTL) Supply Current Power Dissipation Min. differential input voltage swing for differential PECL inputs Differential Serial Output Voltage Swing Input Capacitance 100 1400 570 1.85 Min 2.4 GND 2.0 GN D 0.8 40 600 660 2.3 2600 2600 3 Typ 2.8 .025 Max VDD 0.5 Units V V V V A A mA W mV mV pf VIN = 2.4 V, VDD = Max VIN = .8 V, VDD = Max 1010 Pattern 1010 Pattern See Figure 20. See Figure 19. Conditions VDD = min IOH = -4mA VDD = min IOL = 4mA
July 16, 1999 / Revision A
25
S2202
OUTPUT LOAD
The S2202 serial outputs do not require output pulldown resistors.
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DUAL GIGABIT ETHERNET DEVICE
Figure 17. Serial Input/Output Rise and Fall Time
80% 50% 20% Tr Tf 80% 50% 20%
Figure 20. High Speed Differential Inputs
VDD - 1.3 V 0.01 f
100
Figure 18. TTL Input/Output Rise and Fall Time
+2.0V +0.8V Tr Tf +2.0V +0.8V
0.01 f
Figure 21. Receiver Input Eye Diagram Jitter Mask Figure 19. Serial Output Load
Bit Time
VDD -2.3V 0.01 f
Amplitude
0.01 f
24%
26
July 16, 1999 / Revision A
DUAL GIGABIT ETHERNET DEVICE
Figure 22. Loop Filter Capacitor Connections
S2202
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270 CAP1 22 nf CAP2 270
S2202
July 16, 1999 / Revision A
27
S2202
Ordering Information
PREFIX
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DUAL GIGABIT ETHERNET DEVICE
DEVICE
PACKAGE
S- Integrated Circuit
2202
TB - 156 TBGA
X Prefix
XXXX Device
X Package
IS
O 90 0
RT
IFI
Applied Micro Circuits Corporation * 6290 Sequence Dr., San Diego, CA 92121 Phone: (619) 450-9333 * (800) 755-2622 * Fax: (619) 450-9885 http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright (R) 1999 Applied Micro Circuits Corporation
28
E
D
1
CE
July 16, 1999 / Revision A

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